An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter

In this paper, we propose an improved parallel lattice structure to implement IFFT module in the transmitter of Discrete Multitone (DMT) system. By exploiting the symmetric/anti-symmetric properties of the input symbols, we add a new pre-processing scheme to previous work. By doing so, the iteration number can be halved from 2N to N (N is 256 in DMT). As a result, the clock rate of the IFFT lattice module can be lowered under the same input symbol rate. In addition, the internal registers are also reduced from 4N-4 to 2N-2, and multiplexers in post-processing circuits are all eliminated compared with the previous design. Hence, the proposed method can save more power consumption and further reduce the hardware complexity of the IFFT module. The proposed architecture is regular, modular, and free of global routing. Thus, it is very suitable for VLSI implementation