A parallel architecture for estimating 4th-order cumulants

Author

Lim, J.G. ; Lim, C.C.

Author_Institution

Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

322

Abstract

A novel parallel architecture for estimating computationally intensive 4th-order cumulants is presented. Different from most systolic array implementations, a MIMD array processor is used to efficiently compute the cumulants by exploiting the algorithmic parallelism, reducing operand-fetching operations and by optimising the processing elements´ architectural design. It is shown that by breaking the algorithm into a number of separate stages and reorganising all computations in matrix block form, a significant computational speed-up can be obtained, which increases the applicability of cumulant-based algorithms in a real-time system

Keywords

higher order statistics; parallel architectures; MIMD array processor; estimation algorithm; fourth-order cumulant; parallel architecture; real-time system; Concurrent computing; Design optimization; High performance computing; Parallel architectures; Parallel processing; Radar signal processing; Random variables; Real time systems; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922237

Filename

922237