Interfacing multiple processors in a system-on-chip video encoder

Author

Salminen, Erno ; Hämäläinen, Timo ; Kangas, Tero ; Kuusilinna, Kimmo ; Saarinen, Jukka

Author_Institution

Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

478

Abstract

Interfacing RISC and DSP processors as Intellectual Property blocks for an MPEG-4 baseline video encoder is presented. Our previously presented Heterogeneous IP Block Interconnection (HIBI) architecture is used as a base for contemporary System-on-Chip implementations. Cost effective, general-purpose processor cores and DSPs lacking a native HIBI support need very low-delay interfacing units that are explained in detail in this paper. Interfaces are written in synthesisable VHDL and verified in Mentor Seamless CVE co-verification environment

Keywords

digital signal processing chips; industrial property; reduced instruction set computing; video coding; DSP processor; HIBI architecture; MPEG-4 video encoder; Mentor Seamless CVE co-verification; RISC processor; VHDL; general-purpose processor core; heterogeneous intellectual property block interconnection; interfacing unit; system-on-chip; Bit rate; Computer interfaces; Digital signal processing; Digital signal processing chips; Encoding; Hardware; Intellectual property; Laboratories; Logic; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922278

Filename

922278