An analogue SIMD focal-plane processor array

Author

Dudek, Piotr ; Hicks, Peter J.

Author_Institution

Dept. of Electr. Eng. & Electron., Univ. of Manchester Inst. of Sci. & Technol., UK

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

490

Abstract

A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presented. The architecture is based on a fine-grain software-programmable SIMD array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analogue microprocessor concept. In a 0.6 μm CMOS process the cell size is equal to 98.6 μm×98.6 μm. A prototype 21×21 array chip executes over 1.1 GIPS (Giga Instructions Per Second) while dissipating below 40 mW of power and demonstrates a real-time performance on a variety of early vision tasks

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; focal planes; intelligent sensors; parallel processing; switched current circuits; 0.6 micron; 40 mW; CMOS process; analogue processing elements; cell size; early vision tasks; fine-grain software-programmable SIMD array; focal-plane processor array; grey-scale images; real-time performanc; smart-sensor VLSI circuit; switched-current analogue microprocessor concept; Arithmetic; Cellular neural networks; Circuits; Communication system control; Image processing; Machine vision; Pixel; Power dissipation; Registers; Sensor arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922281

Filename

922281