DocumentCode
1745299
Title
New bit-parallel systolic multipliers for a class of GF(2m )
Author
Lee, Chiou-Yng ; Lu, Erl-Huei ; Lee, Jau-Yien
Author_Institution
Chung Gang Univ., Taiwan
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
578
Abstract
The operations of the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplications over a class of GF(2m) was developed in this paper. The low complexity bit-parallel systolic multiplier is presented. The multiplier has very low latency, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplications over the class of GF(2m) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree m
Keywords
Galois fields; digital arithmetic; multiplying circuits; polynomials; systolic arrays; GF(2m); all one polynomial; bit-parallel systolic multiplier; complexity; cyclic shifting; equally space polynomial; finite field arithmetic; inner product; latency; multiplication algorithm; Clocks; Computer architecture; Computer science; Cryptography; Delay; Digital arithmetic; Electrostatic precipitators; Galois fields; Polynomials; Senior members;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922303
Filename
922303
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