A low power and area efficient FIR filter chip for PRML read channels

This paper proposes a low power and area efficient FIR filter chip for a partial-response maximum likelihood (PRML) disk drive read channel, which is a 6-b, 8-tap FIR filter. The proposed filter employs a parallel processing pipelined architecture. It uses the modified Booth algorithm for multiplication and the compressor logic for addition. The CMOS pass-transistor logic is used for the low power consumption and the single-rail logic is used to reduce the chip area. The proposed filter chip dissipates 120 mW at 100 Hz, 3.3 V power supply and occupies 1.88×1.38 mm². The proposed filter shows about 11% power reduction and about 15% area reduction compared with existing architectures. This chip was fabricated by Hyundai Semiconductor