A low-power high driving ability voltage control oscillator used in PLL

Author

Cheng, Kuo-Hsing ; Yang, Wei-Bin ; Chung, Chun-Fu

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

614

Abstract

Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal´s rise time and fall time rather than on the buffer´s delay time. For these applications we propose a novel voltage controlled oscillator (VCO) with split path CMOS driver. It can be proposed to reduce the total power consumption and phase errors of the PLL. The proposed VCO with the split-path CMOS driver has low power consumption and lower area requirement than that achievable by the traditional tapered CMOS buffer

Keywords

CMOS integrated circuits; buffer circuits; clocks; driver circuits; high-speed integrated circuits; low-power electronics; phase locked loops; voltage-controlled oscillators; clock buffer; high-speed CMOS processor; low-power voltage control oscillator; on-chip phase locked loop; phase error; power consumption; split-path driver; Delay effects; Driver circuits; Energy consumption; Feedback; Frequency conversion; Phase locked loops; Power dissipation; Variable structure systems; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922312

Filename

922312