A low-power high driving ability voltage control oscillator used in PLL

Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal´s rise time and fall time rather than on the buffer´s delay time. For these applications we propose a novel voltage controlled oscillator (VCO) with split path CMOS driver. It can be proposed to reduce the total power consumption and phase errors of the PLL. The proposed VCO with the split-path CMOS driver has low power consumption and lower area requirement than that achievable by the traditional tapered CMOS buffer