• DocumentCode
    1745308
  • Title

    A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level

  • Author

    Heiskanen, Antti ; Mantyniemi, Antti ; Rahkonen, Timo

  • Author_Institution
    Dept. of Electr. Eng., Oulu Univ., Finland
  • Volume
    4
  • fYear
    2001
  • fDate
    6-9 May 2001
  • Firstpage
    626
  • Abstract
    A 30 MHz, 30 mW, 0.3 mm2 DDS clock generator circuit with time domain interpolation and -50 dBc spurious signal level has been designed. The sine look-up-table and D/A converter of the conventional DDS have been replaced by a three-step digitally programmable delay generator with 130 ps resolution. This increases the effective sampling frequency to 7.68 GHz, and that´s why no reconstruction filters are needed to create output square wave clock signal
  • Keywords
    clocks; direct digital synthesis; interpolation; pulse generators; 30 MHz; 30 mW; 7.68 GHz; DDS clock generator; effective sampling frequency; output square wave clock signal; spurious level; sub-ns time domain interpolator; three-step digitally programmable delay generator; Circuits; Clocks; Delay; Filters; Frequency; Interpolation; Sampling methods; Signal design; Signal generators; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    0-7803-6685-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2001.922315
  • Filename
    922315
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1745308