DocumentCode
1745313
Title
A low cost 2-D inverse discrete cosine transform design for image compression
Author
Guo, Jiun-In
Author_Institution
Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miao-Li, Taiwan
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
658
Abstract
This paper proposes a low cost 2-D inverse discrete cosine transform (IDCT) for image compression by using cyclic convolution and adder-based implementation. We formulate the 1-D IDCT into cyclic convolution and carry out the multiplications through adders by using the concept of common sub-expression sharing. The proposed 2-D IDCT design costs 7413 gates plus 1024 bits of memory with 66 MHz throughput based on a 0.35 μm CMOS technology
Keywords
CMOS logic circuits; adders; convolution; data compression; discrete cosine transforms; image coding; 0.35 micron; 2D inverse discrete cosine transform; 66 MHz; CMOS technology; adder; common sub-expression sharing; cyclic convolution; image compression; CMOS technology; Circuits; Costs; Discrete cosine transforms; Encoding; Equations; Hardware; Image coding; Multiplexing; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922323
Filename
922323
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