A CAD tool for architecture level exploration and automatic generation of RNS converters

The analysis and implementation of a CAD tool that can generate the structural description of converters for the Residue Arithmetic System (RNS), assisting the engineer in the architecture level exploration, is presented. The above description is based on a previous proposed architecture, which has been reported as an efficient known to date in terms of area and delay. The outputs of the tool are: (i) abstract but precise hardware characteristics of the converter being designed in order to have a fast estimation of its efficiency and (ii) a synthesizable structural VHDL description for this converter, which can be the input to a VLSI design environment (e.g. Cadence, Synopsis) in order to take the actual silicon implementation. The proposed tool was implemented in C++ language and is available for PC and HP platforms