VLSI architecture of dynamically reconfigurable hardware-based cipher

Author

Mitsuyama, Yukio ; Andales, Zaldy ; Onoye, Takao ; Shirakawa, Isao

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

734

Abstract

This paper describes a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called Chameleon, in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by the 0.6 μm CMOS 3LM technology, using 65.6 K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in mobile computing

Keywords

CMOS digital integrated circuits; VLSI; cryptography; iterative methods; mobile computing; reconfigurable architectures; 0.6 micron; 128 bit; 317.5 Mbit/s; 64 bit; CMOS 3LM technology; Chameleon; VLSI architecture; dynamically reconfigurable hardware-based cipher; encryption/decryption process; iterations; mobile computing; throughput; CMOS technology; Computer architecture; Cryptography; Hardware; Information systems; Mobile computing; Registers; Systems engineering and theory; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922342

Filename

922342