DocumentCode
1745327
Title
ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique
Author
Ker, Ming-Dou ; Chen, Tung-Yung ; Chung-Yu Win
Author_Institution
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
754
Abstract
A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 μm/0.3 μm can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique
Keywords
CMOS integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit reliability; 0.18 micron; 3.3 kV; ESD protection design; HBM ESD level; on-chip protection circuits; robustness; salicide CMOS technology; substrate-triggered technique; CMOS process; CMOS technology; Circuits; Electrostatic discharge; Fingers; MOS devices; Protection; Robustness; Silicides; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922347
Filename
922347
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