Title :
Split-Gate Logic circuits for multi-threshold technologies
Author :
Elrabaa, Muhammad E S ; Elmasry, Mohamed I.
Author_Institution :
Dept. of Electr. Eng., United Arab Emirates Univ., Al-Ain, United Arab Emirates
Abstract :
A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SG-DVT) logic, are devised. Their performance is compared to that of all-low-Vt, all-high-Vt, and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits, lower leakage (both stand-by and active) than other dual-Vt circuits, and lower leakage dependency on logic block input patterns
Keywords :
CMOS logic circuits; threshold logic; SG-DVT logic; active leakage; delay; dual-Vt static CMOS circuit; energy consumption; multi-threshold technology; split-gate logic circuit; stand-by leakage; CMOS logic circuits; CMOS technology; Energy consumption; Feedback control; Leakage current; Logic circuits; MOS devices; Split gate flash memory cells; Threshold voltage; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922358
