A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic

Author

Dumonteix, Yannick ; Bajot, Yann ; Mehrez, Habib

Author_Institution

ASIM Lab., Paris VI Univ., France

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

878

Abstract

This paper presents the design of a fast and low power consumption distance computation unit : Σ_i(A_i-B_i)². It is dedicated to the digital RBF neural network implementation. The proposed architecture is composed of two parts. The first computes the distance (A_i-B_i)², and the second performs the sum of these distances. It is based on an efficient squarer in redundant arithmetic. Thank to this operator, the distance measure circuits developed offer better performances than those based on classical arithmetic. The average gain is equal to 11% in delay and 18% in power consumption

Keywords

low-power electronics; neural chips; radial basis function networks; redundant number systems; circuit architecture; delay; digital RBF neural network; fast low-power distance computation unit; power consumption; redundant arithmetic; squaring unit; Arithmetic; Computer architecture; Computer networks; Delay; Electronic mail; Energy consumption; Laboratories; Neural networks; Neurons; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922378

Filename

922378