DocumentCode
1745354
Title
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT
Author
Lee, Chi Wai ; Choy, Chiu-Sing ; Butas, Jan ; Chan, Cheong-Fat
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
910
Abstract
This paper presents a pipelined dataflow architecture for asynchronous systems, and a small micro-coded processor is constructed to realize this architecture. This pipelined dataflow approach allows different arithmetic units to operate at the same time and thus a shorter computation time and higher throughput rate can be achieved. This proposed architecture is suitable for DSP applications and an implementation of Discrete Cosine Transform (DCT) is shown at the end of this paper
Keywords
asynchronous circuits; data flow computing; digital signal processing chips; discrete cosine transforms; pipeline arithmetic; DCT; DSP applications; arithmetic units; computation time; pipelined dataflow small micro-coded asynchronous processor; throughput rate; Asynchronous circuits; Clocks; Communication system control; Control systems; Delay; Discrete cosine transforms; Pipeline processing; Signal generators; Signal processing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922386
Filename
922386
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