Cache energy reduction by dual voltage supply

This paper presents a novel architectural technique to reduce energy dissipation in caches. Unlike existing approaches, which concentrate on lowering the cache capacitance and the number of accesses, the proposed technique exploits a new freedom in cache design, namely the voltage per access. In a block-buffered cache, the loading capacitance operated on the cache-hit is much less than the capacitance operated on the cache-miss, so the given clock cycle time is inefficiently exploited during the hit. We propose to trade-off the unused cycle time with the supply voltage. lowering the voltage level on the cache-hit and increasing it on the cache-miss. Experiments show that the approach can save up to 60% of cache energy without large performance and area overhead