A methodology for testing high-performance circuits at arbitrarily low test frequency

Author

Nummer, Muhammad ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

2001

fDate

2001

Firstpage

68

Lastpage

74

Abstract

This paper presents a methodology for testing high performance circuits with a low-speed clock in test mode. Using this technique, the frequency of the 50% duty cycle test mode clock can be reduced with virtually no lower limit. This poses very little requirements on automatic test equipment (ATE) and facilitates the testing process. A CMOS implementation that achieves 50 ps accuracy is also presented. This technique targets designs using design for testability (DFT) and/or built-in self test (BIST) techniques

Keywords

CMOS logic circuits; VLSI; built-in self test; design for testability; fault diagnosis; flip-flops; logic testing; sequential circuits; CMOS implementation; arbitrarily low test frequency; automatic test equipment; built-in self test; design for testability; high-performance circuits; low-speed clock; test mode; Automatic testing; Built-in self-test; CMOS technology; Circuit testing; Clocks; Costs; Delay; Design for testability; Frequency; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001

Conference_Location

Marina Del Rey, CA

Print_ISBN

0-7695-1122-8

Type

conf

DOI

10.1109/VTS.2001.923420

Filename

923420