Title :
Scan wheel-a technique for interfacing a high speed scan-path with a slow speed tester
Author :
Bhavsar, Dilip K.
Author_Institution :
Alpha Dev. Group, Compaq Comput. Corp., Shrewsbury, MA, USA
Abstract :
A novel interface architecture allows slow-speed test equipment to control and access scan registers operating at the full clock rate of the chip or the system. The architecture requires simple on-chip hardware and works with a minimal number of chip pins
Keywords :
automatic test pattern generation; boundary scan testing; design for testability; fault diagnosis; logic testing; ATPG; DFT; chip pins; fault diagnosis; full clock rate; high speed scan-path; interface architecture; on-chip hardware; scan registers; scan wheel; slow speed tester; Circuit testing; Clocks; Computer architecture; Control systems; Delay; Pins; Registers; System testing; Test equipment; Wheels;
Conference_Titel :
VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
Conference_Location :
Marina Del Rey, CA
Print_ISBN :
0-7695-1122-8
DOI :
10.1109/VTS.2001.923424
