Analysis of testing methodologies for custom designs in PowerPCTM microprocessor

Custom circuits, in contrast to those synthesized by automatic tools, are manually designed blocks of which performance is critical to the full chip operation. Testing these blocks represents a major DFT challenge and hence, a crucial time-to-market factor in microprocessor design flow. This paper compares three industry-adopted methodologies for testing custom blocks. Pros and cons are analyzed and discussed based on factors such as stability of the methodologies, resulting sizes of gate-level models, ATPG process, and testing quality in terms of non-target defect detection. Experience and results from a recent PowerPC microprocessor are reported