Chip clustering with mutual information on multiple clock tests and its application to yield tuning

Process variation in advanced CMOS processes is an increasingly important influence in test efficiency, design optimization and yield learning. Yet, there is no efficient test process to assist designers to categorize chips for analyzing the influence of variation on their respective objectives. In this paper, we propose a test process and an analysis method with multiple clocks. Each chip is first tested with selected paths on multiple clocks (smaller than target chip clock). And the test results of outputs on selected paths are recorded and further used as a signature to determine the class of which the chip belongs to. As an application, we use the proposed scheme to sort chips into different categories and assign a supply voltage configuration for each category to fix chip timings. In experiments, results show that testing with one or two clocks, the method can obtain chip yields of 88-99% (original yield is 9-34%) with an increase of 4-25% nominal dynamic powers, while full-swing voltage setup would require 50% increase of powers.