• DocumentCode
    174637
  • Title

    Dynamic associative caches: Reducing dynamic energy of first level caches

  • Author

    Dayalan, Karthikeyan ; Ozsoy, Meltem ; Ponomarev, Dmitry

  • Author_Institution
    State Univ. of New York at Binghamton, Binghamton, NY, USA
  • fYear
    2014
  • fDate
    19-22 Oct. 2014
  • Firstpage
    118
  • Lastpage
    124
  • Abstract
    We propose Dynamic Associative Cache (DAC) - a low complexity design to improve the energy-efficiency of the data caches with negligible performance overhead. The key idea of DAC is to perform dynamic adaptation of cache associativity - switching the cache operation between direct-mapped and set-associative regimes - during the program execution. To monitor the program needs in terms of cache associativity, the DAC design employs a subset of shadow tags: when the main cache operates in the set-associative mode, the shadow tags operate in the direct-mapped mode and vice versa. The difference in the hit rates between the main tags and the shadow tags is used as an indicator for the cache mode switching. We show that DAC performs most of its accesses in the direct-mapped mode resulting in significant energy savings, at the same time maintaining performance close to that of set-associative L1 D-cache.
  • Keywords
    cache storage; content-addressable storage; low-power electronics; cache associativity; data cache efficiency; direct mapped regime; dynamic associative cache; dynamic energy reduction; first level cache; low complexity design; set associative regime; set-associative mode; Arrays; Benchmark testing; Context; Monitoring; Program processors; Radiation detectors; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2014 32nd IEEE International Conference on
  • Conference_Location
    Seoul
  • Type

    conf

  • DOI
    10.1109/ICCD.2014.6974693
  • Filename
    6974693