Title : 
Pattern-restricted design at 10nm and beyond
         
        
            Author : 
Ghaida, Rani S. ; Badr, Youakim ; Gupta, Puneet
         
        
            Author_Institution : 
Technol. Dev. Div., GLOBALFOUNDRIES, Santa Clara, CA, USA
         
        
        
        
        
        
            Abstract : 
Manufacturing has been incapable of keeping up with Moore´s law without significantly increasing process variability and imposing massive geometric restrictions on design. This paper highlights the design impact of variability and geometric constraints - including traditional design rules and pattern-scale constraints - and describes our approach for evaluating and enforcing pattern-scale restrictions on design.
         
        
            Keywords : 
integrated circuit design; Moore´s law; geometric constraints; pattern-restricted design; pattern-scale constraints; size 10 nm; Delays; Layout; Manufacturing; Predictive models; Routing; Transistors;
         
        
        
        
            Conference_Titel : 
Computer Design (ICCD), 2014 32nd IEEE International Conference on
         
        
            Conference_Location : 
Seoul
         
        
        
            DOI : 
10.1109/ICCD.2014.6974698