Title :
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length
Author :
Shioya, R. ; Ando, H.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Nagoya Univ., Nagoya, Japan
Abstract :
A renaming logic is a high-cost module in a superscalar processor, and it consumes significant energy. For mitigating this, renamed trace cache (RTC), which caches renamed operands, was proposed. However, conventional RTCs have several problems such as low capacity-efficiency, large hardware overhead and insufficient caching of renamed operands. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands whose distances from producers outside traces are short, and it solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead compared to a conventional processor.
Keywords :
cache storage; energy conservation; energy consumption; logic circuits; RTC; SGRTC; dependent path length reduction; energy consumption; energy efficiency improvement; high-cost module; insufficient caching; large hardware overhead; low capacity-efficiency; renamed operands; renaming logic; semiglobal renamed trace cache; superscalar processor; Arrays; Energy consumption; Hardware; Pipelines; Proposals; Random access memory; Registers;
Conference_Titel :
Computer Design (ICCD), 2014 32nd IEEE International Conference on
Conference_Location :
Seoul
DOI :
10.1109/ICCD.2014.6974714