• DocumentCode
    1746829
  • Title

    Utilizing surplus timing for power reduction

  • Author

    Hamada, Mototsugu ; Ootaguro, Yukio ; Kuroda, Tadahiro

  • Author_Institution
    Syst. LSI Res. & Dev. Center, Toshiba Corp., Japan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    89
  • Lastpage
    92
  • Abstract
    Multiple Vdd´s, multiple Vth´s, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd´s, Vth´s, and W´s are derived, as well as knowledge for future design
  • Keywords
    integrated circuit design; low-power electronics; timing; multiple power supplies; multiple threshold voltages; multiple transistor width; noncritical paths; power reduction; surplus timing; Capacitance; Delay effects; Frequency; Integrated circuit interconnections; Large scale integration; Power dissipation; Power supplies; Threshold voltage; Thumb; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits, 2001, IEEE Conference on.
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-6591-7
  • Type

    conf

  • DOI
    10.1109/CICC.2001.929730
  • Filename
    929730
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1746829