Sp2V: accelerating post-layout spice simulation using Verilog gate-level modeling

We propose a system for accelerating post-layout simulation of digital circuits. The conventional method using standard cells for layout generation leads us to perform post-layout simulation of digital circuits at the gate-level rather than the transistor or switch level. In our method, first an accurate model of each standard cell or gate is described in Verilog HDL. Then the Verilog model of design, which uses instances of gates, is generated from the corresponding Spice description through an automatic method. The result of the proposed method has a simulation gain of one to two orders of magnitude with exact functionality and a maximum 15% timing accuracy less than Spice simulation, as well as providing a complete design into high-level description, which alleviates many SPICE problems like convergence and other failures especially in large designs