Checkpointing and error recovery in a uniprocessor system with on-chip cache

Checkpointing and rollback error recovery technique used in fault-tolerant systems allows recovery from errors without a need for a global restart of computation. This paper presents two efficient and low-cost schemes to handle soft (transient) errors in a uniprocessor system with on-chip cache memory. These user-transparent schemes are implemented in hardware and require negligible hardware overhead in the designs of processor and cache memory. The first scheme uses a write-through policy for on-chip cache and a checkpoint is established on each write-through; while the second scheme offers improvement over the working of the first scheme by including a second level cache in the memory hierarchy. A simple mathematical model is developed and a trade-off analysis between two schemes is presented