DocumentCode :
1747779
Title :
Self-repairable EPLDs. II. Advanced self-repairing methodology
Author :
Lee, Chong H. ; Perkowski, Marek A. ; Hall, Douglas V. ; Jun, David S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
Volume :
1
fYear :
2001
fDate :
2001
Firstpage :
616
Abstract :
For Part I, see 2nd NASA/DoD Workshop on Evolvable Hardware, pp.183-193 (July 2000). Describes an advanced self-testing, self-repair architecture and methodology for Lattice Logic Corp.´s GAL (generic array logic) devices, which are EPLDs (electrically programmable logic devices) that are used in high-security and safety applications, such as aerospace systems, military systems or medical instruments. We describe a new “column re-use” method that, if possible, exchanges a faulty GAL column with a column that needs the same programming as supplied by the faulty column and then reprograms the freed column to replace the faulty one. In contrast, our former self-repairing methodology, called the “column replacement method with extra columns”, described Part I, just discarded each faulty column and replaced it with an extra column. Our evaluation methodology shows that the lifetime of a GAL that uses the `column re-use´ method is longer than the lifetime of a GAL that uses just the `column replacement´ method or the `no self-repair´ method. Our results also give information on how many extra columns a GAL needs to reach a lifetime goal, in terms of the simulation looping time, until the GAL is not useful any more. Our system is also applicable to other devices, such as FPGAs (field programmable gate arrays)
Keywords :
fault tolerance; integrated circuit reliability; maintenance engineering; programmable logic arrays; FPGA; Lattice Logic Corp.; column replacement method; column reuse method; device lifetime; extra columns; faulty column replacement; field programmable gate arrays; generic array logic devices; high-safety applications; high-security applications; programming; self-repair architecture; self-repairable EPLD; self-repairing methodology; self-testing; simulation looping time; Aerospace safety; Built-in self-test; Field programmable gate arrays; Hardware; Lattices; Logic devices; Logic programming; NASA; Programmable logic arrays; Programmable logic devices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Evolutionary Computation, 2001. Proceedings of the 2001 Congress on
Conference_Location :
Seoul
Print_ISBN :
0-7803-6657-3
Type :
conf
DOI :
10.1109/CEC.2001.934448
Filename :
934448
Link To Document :
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