DocumentCode
1747780
Title
A hardware implementation of the Compact Genetic Algorithm
Author
Aporntewan, Chatchawit ; Chongstitvatana, Prabhas
Author_Institution
Dept. of Comput. Eng., Chulalongkorn Univ., Bangkok, Thailand
Volume
1
fYear
2001
fDate
2001
Firstpage
624
Abstract
We propose a hardware implementation of the Compact Genetic Algorithm (GA). The design is realized using the Verilog hardware description language (HDL) and then fabricated on an FPGA. Our design, though simple, runs about 1000 times faster than the software executing on a workstation. An alternative hardware for linkage learning is also proposed in order to enhance the capability of the Compact GA to solve highly deceptive problems
Keywords
field programmable gate arrays; firmware; genetic algorithms; hardware description languages; special purpose computers; Compact Genetic Algorithm; FPGA; Verilog hardware description language; deceptive problems; execution speed; hardware implementation; linkage learning; Acceleration; Couplings; Field programmable gate arrays; Frequency; Genetic algorithms; Genetic engineering; Genetic mutations; Hardware design languages; Random number generation; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Evolutionary Computation, 2001. Proceedings of the 2001 Congress on
Conference_Location
Seoul
Print_ISBN
0-7803-6657-3
Type
conf
DOI
10.1109/CEC.2001.934449
Filename
934449
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