A memory efficient motion estimator for three step search block-matching algorithm

Author

Lai, Yeong-Kang

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Dong-Hua Univ., Taiwan

fYear

2001

fDate

2001

Firstpage

166

Lastpage

167

Abstract

This paper describes an memory efficient array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify the control scheme and reduce latency, respectively. The results demonstrate that the array architecture with memory efficient scheme requires a smaller memory and low input ports

Keywords

VLSI; cellular arrays; data compression; digital signal processing chips; image matching; integrated memory circuits; motion estimation; search problems; video coding; VLSI; comparator-tree structure; data-rings; hierarchical search block-matching algorithm; latency reduction; low input ports; memory efficient array architecture; memory efficient motion estimator; memory organization; raster-scanned data flow; three step search block-matching algorithm; video compression; Clocks; Communication system control; Computer science; Delay; Image storage; Motion estimation; Postal services; Transform coding; Video compression; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2001. ICCE. International Conference on

Conference_Location

Los Angeles, CA

Print_ISBN

0-7803-6622-0

Type

conf

DOI

10.1109/ICCE.2001.935258

Filename

935258