DocumentCode
1747801
Title
Parallel architecture for MPEG-4 visual ACE profile
Author
Adar, Rutie ; Akerib, Avidan ; Mehrbians, Raphael
fYear
2001
fDate
2001
Firstpage
180
Lastpage
181
Abstract
We present an innovative architecture for real-time video processing which is capable of manipulating 8 thousand pixels in parallel, and which uses the performance represented by this level of parallelism to achieve MPEG-4 visual ACE profile for real time interlaced CCIR-601 compression
Keywords
associative processing; code standards; data compression; digital signal processing chips; parallel architectures; telecommunication standards; video coding; MPEG-4 visual ACE profile; parallel architecture; parallel processing; pixels; real time interlaced CCIR-601 compression; real-time video encoding; real-time video processing; Associative processing; Central Processing Unit; Codecs; Digital signal processing chips; Discrete cosine transforms; Hardware; Internet; MPEG 4 Standard; Parallel architectures; Video on demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2001. ICCE. International Conference on
Conference_Location
Los Angeles, CA
Print_ISBN
0-7803-6622-0
Type
conf
DOI
10.1109/ICCE.2001.935264
Filename
935264
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