Title :
Estimation of speed, area, and power of parameterizable, soft IP
Author :
Sanghavi, Jagesh ; Wang, Albert
Author_Institution :
Tensilica Inc., USA
Abstract :
We present a new approach to estimate speed, area, and power of a parameterizable, soft IP. By running the ASIC implementation flow only on selected configurations, we predict the performance for any arbitrary configuration. We exploit performance function decomposability to address the combinatorial explosion challenge. The estimator has been used successfully to configure Xtensa processor cores for numerous embedded SOC designs.
Keywords :
VLSI; application specific integrated circuits; industrial property; integrated circuit design; logic CAD; software libraries; ASIC implementation flow; Xtensa processor cores; combinatorial explosion challenge; embedded SOC designs; parameterizable IP; performance function decomposability; soft IP; Application specific integrated circuits; Costs; Digital signal processing; Explosions; Extraterrestrial measurements; Feedback; Parameter estimation; Permission; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2001. Proceedings
Print_ISBN :
1-58113-297-2
DOI :
10.1109/DAC.2001.156103
