DocumentCode :
1747905
Title :
Computing logic-stage delays using circuit simulation and symbolic Elmore analysis
Author :
McDonald, Clayton B. ; Bryant, Randal E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2001
fDate :
2001
Firstpage :
283
Lastpage :
288
Abstract :
The computation of logic-stage delays is a fundamental sub-problem for many EDA tasks. Although accurate delays can be obtained via circuit simulation, we must estimate the input assignments that will maximize the delay. With conventional methods, it is not feasible to estimate the delay for all input assignments on large sub-networks, so previous approaches have relied on heuristics. We present a symbolic algorithm that enables efficient computation of the Elmore delay under all input assignments and delay refinement using circuit-simulation. We analyze the Elmore estimate with three metrics using data extracted from symbolic timing simulations of industrial circuits.
Keywords :
circuit CAD; circuit simulation; delays; logic simulation; symbol manipulation; timing; EDA tasks; circuit simulation; delay refinement; heuristics; industrial circuits; input assignments; logic-stage delays; symbolic Elmore analysis; symbolic algorithm; symbolic timing simulations; Analytical models; Circuit analysis; Circuit analysis computing; Circuit simulation; Computational modeling; Data mining; Delay estimation; Electronic design automation and methodology; Refining; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings
ISSN :
0738-100X
Print_ISBN :
1-58113-297-2
Type :
conf
DOI :
10.1109/DAC.2001.156152
Filename :
935521
Link To Document :
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