• DocumentCode
    1747906
  • Title

    A new gate delay model for simultaneous switching and its applications

  • Author

    Chen, Liang-Chi ; Gupta, Sandeep K. ; Breuer, Melvin A.

  • Author_Institution
    Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    289
  • Lastpage
    294
  • Abstract
    We present a new model to capture the delay phenomena associated with simultaneous to-controlling transitions. The proposed delay model accurately captures the effect of the targeted delay phenomena over a wide range of transition times and skews. It also captures the effects of more variables than table lookup methods can handle. The model helps improve the accuracy of static timing analysis, incremental timing refinement, and timing-based ATPG.
  • Keywords
    automatic test pattern generation; combinational circuits; delays; logic gates; logic testing; timing; delay phenomena; gate delay model; incremental timing refinement; simultaneous switching; static timing analysis; targeted delay phenomena; timing-based ATPG; to-controlling transitions; transition times; Accuracy; Automatic test pattern generation; Benchmark testing; Circuits; Computational modeling; Delay effects; Performance analysis; Permission; Table lookup; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings
  • ISSN
    0738-100X
  • Print_ISBN
    1-58113-297-2
  • Type

    conf

  • DOI
    10.1109/DAC.2001.156153
  • Filename
    935522