Title :
Fault characterizations and design-for-testability technique for detecting IDDQ faults in CMOS/BiCMOS circuits
Author :
Raahemifar, Kaamran ; Ahmadi, Majid
Author_Institution :
Electr. & Comput. Eng. Dept., Ryerson Polytech. Inst., Toronto, Ont., Canada
Abstract :
This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause lDDQ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.
Keywords :
BiCMOS logic circuits; CMOS logic circuits; design for testability; fault location; integrated circuit testing; logic design; logic testing; BiCMOS circuits; BiCMOS logic families; CMOS circuits; CMOS logic families; DFT technique; IDDQ faults detection; bridging faults; delay faults; design-for-testability technique; open defects; shorts; simulation-based fault characterization; stuck-open faults; BiCMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Fault detection; Permission; Semiconductor device modeling;
Conference_Titel :
Design Automation Conference, 2001. Proceedings
Print_ISBN :
1-58113-297-2
DOI :
10.1109/DAC.2001.156157
