Inductance 101: analysis and design issues

With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. In this paper we give a tutorial overview of the analysis and design issues related to on-chip inductance effects. We explain the complexity of the current flow in VLSI circuits. We discuss the applicability of the PEEC approach in a derailed circuit model of the signal and power grid interconnect, switching devices, power pads and the package. Further we explain techniques that can be used to speed-up simulation of the large PEEC model. We then discuss a simplified model that uses the so-called loop inductance approach, and compare it with the detailed model. We present experimental results, obtained from simulations of industrial circuits, for both the PEEC and loop models. We also cover design techniques that can help tackle the on-chip inductance issues.