DocumentCode :
1747919
Title :
Latency and latch count minimization in wave steered circuits
Author :
Singh, A. ; Mukherjee, A. ; Marek-Sadowska, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
2001
fDate :
22-22 June 2001
Firstpage :
383
Lastpage :
388
Abstract :
Wave steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. Wave steered circuits inherently utilize latches in order to guarantee the correct signal arrival times at the inputs of these synthesized structures and maintain the high throughput of operation. In this paper, we show a method of reordering signals to achieve minimum circuit latency for wave steered circuits and propose an integer linear programming (ILP) formulation for scheduling and retiming these circuits to minimize the number of latches for minimum latency. Experimental results show that in 0.25 /spl mu/m CMOS technology, as much as 33.2% reduction in latch count, at minimum latency, can be achieved over unoptimized wave steered circuits operating at 500 MHz.
Keywords :
CMOS logic circuits; binary decision diagrams; circuit layout CAD; flip-flops; integer programming; integrated circuit layout; linear programming; logic CAD; minimisation of switching nets; timing; 0.25 micron; 500 MHz; CMOS technology; design methodology; high throughput circuits; integer linear programming; latch count minimization; layout friendly synthesized structures; retiming; scheduling; signal arrival times; wave steered circuits; CMOS technology; Circuit synthesis; Delay; Design methodology; Integer linear programming; Latches; Minimization; Signal synthesis; Silicon; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings
Conference_Location :
Las Vegas, NV, USA
ISSN :
0738-100X
Print_ISBN :
1-58113-297-2
Type :
conf
DOI :
10.1109/DAC.2001.156170
Filename :
935539
Link To Document :
بازگشت