DocumentCode
1747952
Title
A hardware/software co-design flow and IP library based of Simulink TM
Author
Reynari, L.M. ; Cucinotta, F. ; Serra, A. ; Lavagno, L.
Author_Institution
Dipartimento di Elettronica, Politecnico di Torino, Italy
fYear
2001
fDate
2001
Firstpage
593
Lastpage
598
Abstract
This paper describes a design flow for data-dominated embedded systems. We use The Mathworks´ SimulinkTM environment for functional specification and algorithmic analysis. We developed a library of Simulink blocks, each parameterized by design choices such as implementation (software, analog or digital hardware, ...) and numerical accuracy (resolution, S/N ratio). Each block is equipped with empirical models for cost (code size, chip area) and performance (timing, energy), based on surface fitting from actual measurements. We also developed an analysis toolbox that quickly evaluates algorithm and parameter choices performed by the designer and presents the results for fast feedback. The chosen block netlist is then ready for implementation, by using a customization of The Mathworks´ Real Time WorkshopTM to generate a VHDL netlist for FPGA implementation, as well as embedded software for DSP implementation.
Keywords
embedded systems; field programmable gate arrays; hardware description languages; hardware-software codesign; industrial property; performance evaluation; surface fitting; DSP implementation; FPGA; IP library; Mathworks; Real Time Workshop; S/N ratio; Simulink; VHDL netlist; algorithmic analysis; analysis toolbox; cost; embedded software; empirical models; functional specification; hardware/software co-design; performance; resolution; surface fitting; Algorithm design and analysis; Area measurement; Costs; Embedded software; Embedded system; Energy resolution; Hardware; Software libraries; Surface fitting; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings
ISSN
0738-100X
Print_ISBN
1-58113-297-2
Type
conf
DOI
10.1109/DAC.2001.156209
Filename
935578
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