• DocumentCode
    1747969
  • Title

    False coupling interactions in static timing analysis

  • Author

    Arunachalam, Ravishankar ; Blanton, R.D. ; Pileggi, Lawrence T.

  • Author_Institution
    IBM Corp., Austin, TX, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    726
  • Lastpage
    731
  • Abstract
    Neighboring line switching can contribute to a large portion of the delay of a line for today´s deep submicron designs. In order to avoid excessive conservatism in static timing analysis, it is important to determine if aggressor lines can potentially switch simultaneously with the victim. In this paper, we present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. We present results on several benchmark circuits that show the value of considering functional information to reduce the conservatism associated with worst-case coupled line switching assumptions during static timing analysis.
  • Keywords
    VLSI; automatic test pattern generation; hazards and race conditions; integrated circuit design; integrated circuit interconnections; logic testing; timing; ATPG-based approach; aggressor lines; benchmark circuits; deep submicron designs; dynamic hazards; false coupling interactions; functional information; glitches; neighboring line switching; static hazards; static timing analysis; worst-case coupled line switching assumptions; Circuit noise; Coupling circuits; Delay lines; Hazards; Information analysis; Parasitic capacitance; Permission; Switches; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings
  • ISSN
    0738-100X
  • Print_ISBN
    1-58113-297-2
  • Type

    conf

  • DOI
    10.1109/DAC.2001.156232
  • Filename
    935601