Fault Models and Test Methods for Subthreshold SRAMs

Author

Chen-Wei Lin ; Hung-Hsin Chen ; Hao-Yu Yang ; Chin-Yuan Huang ; Chao, Mango C.-T ; Rei-Fu Huang

Author_Institution

Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

62

Issue

3

fYear

2013

fDate

Mar-13

Firstpage

468

Lastpage

481

Abstract

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.

Keywords

CMOS memory circuits; SRAM chips; amplifiers; decoding; fault diagnosis; integrated circuit design; integrated circuit testing; SRAM fault model; SRAM test method; decoder faults; open defect faulty behavior; sense amplifiers; subthreshold SRAM design; threshold-voltage mismatch; Circuit faults; MOSFETs; Random access memory; Resistance; Stability analysis; Stress; SRAM; open defect; stability fault; sub-V_{th}; subthreshold; testing;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.2011.252

Filename

6112749