DocumentCode
1748590
Title
Exploring and exploiting wire-level pipelining in emerging technologies
Author
Niemier, Michael Thaddeus ; Kogge, Peter M.
Author_Institution
Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
fYear
2001
fDate
2001
Firstpage
166
Lastpage
177
Abstract
Pipelining is a technique that has long since been considered fundamental by computer architects. However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels-particularly the device level. How this affects circuits and the relationship between their timing, architecture, and design will be studied in the context of an inherently self-latching nanotechnology termed quantum cellular automata (QCA). Results indicate that this nanotechnology offers the potential for “free” multi-threading and “processing-in-wire”. All of this could be accomplished in a technology that could be almost three orders of magnitude denser than an equivalent design fabricated in a process at the end of the CMOS curve
Keywords
cellular automata; nanotechnology; pipeline processing; timing; CMOS curve; computer architects; emerging technologies; multi-threading; nanoelectronics; processing-in-wire; quantum cellular automata; wire-level pipelining; CMOS technology; Circuits; Computer science; Josephson junctions; Logic functions; Nanoelectronics; Nanotechnology; Pipeline processing; Quantum cellular automata; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 2001. Proceedings. 28th Annual International Symposium on
Conference_Location
Goteborg
ISSN
1063-6897
Print_ISBN
0-7695-1162-7
Type
conf
DOI
10.1109/ISCA.2001.937445
Filename
937445
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