DocumentCode
1749061
Title
On higher order noise immune perceptrons
Author
Beiu, Valeriu
Author_Institution
Washington State Univ., Pullman, WA, USA
Volume
1
fYear
2001
fDate
2001
Firstpage
246
Abstract
Details a systematic method for significantly enhancing the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the linearly separable (threshold) function to be implemented. It follows that linearly separable functions can be computed with high noise immunity by higher order perceptrons. Simulation results support our theoretical claims. Finally, two methods for drastically reducing the dissipated power of such higher order perceptron gates down to <50%, and respectively <10% are suggested
Keywords
VLSI; logic gates; neural chips; perceptrons; threshold elements; Boolean form; dissipated power; higher order noise immune perceptrons; linearly separable threshold function; noise margins; very fast threshold gates; Algebra; Books; Boolean functions; Computational modeling; Logic circuits; Logic design; Logic functions; Logic gates; Mathematics; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 2001. Proceedings. IJCNN '01. International Joint Conference on
Conference_Location
Washington, DC
ISSN
1098-7576
Print_ISBN
0-7803-7044-9
Type
conf
DOI
10.1109/IJCNN.2001.939025
Filename
939025
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