DocumentCode :
1749434
Title :
A memory reduction scheme for multi-channel echo canceller implementation
Author :
Choo, Chang Y. ; Elabd, H.
Author_Institution :
RealChip Commun., Sunnyvale, CA, USA
Volume :
5
fYear :
2001
fDate :
2001
Firstpage :
3301
Abstract :
One of the critical resources of the multi-channel echo canceller is the memory that stores both tapped delay lines of voice data and filter tap coefficients. A simple variable-length/run-length coding scheme for reducing coefficient memory for multi-channel echo cancellers is proposed. We also describe the corresponding memory system architecture. Simulations based on a bit-accurate Matlab model show that the proposed scheme is effective
Keywords :
echo suppression; memory architecture; runlength codes; speech processing; variable length codes; bit-accurate Matlab model; coefficient memory reduction; filter tap coefficients; memory system architecture; multi-channel echo canceller; runlength coding; tapped delay lines; variable length coding; voice data; Delay lines; Digital signal processing; Digital signal processing chips; Echo cancellers; Finite impulse response filter; Internet telephony; Least squares approximation; Mathematical model; Memory architecture; Scalability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on
Conference_Location :
Salt Lake City, UT
ISSN :
1520-6149
Print_ISBN :
0-7803-7041-4
Type :
conf
DOI :
10.1109/ICASSP.2001.940364
Filename :
940364
Link To Document :
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