Power efficient semi-automatic instruction encoding for application specific instruction set processors

Author

Glokler, Tilman ; Bitterlich, Stefan

Author_Institution

Inst. for Integrated Signal Process. Syst., Aachen Univ. of Technol., Germany

Volume

2

fYear

2001

fDate

2001

Firstpage

1169

Abstract

A novel design methodology for the implementation of control units for application specific instruction set processors (ASIPS) is described. This methodology uses automatic instruction encoding and semi-automatic generation of the hardware instruction decoder to speed up the ASIP design. Significant power savings due to optimized instruction encoding are achieved. Results for ICORE (ISS-Core), which is an ASIP for digital video broadcasting algorithms of Infineon Technologies, demonstrate the efficiency and applicability of this approach

Keywords

application specific integrated circuits; digital signal processing chips; digital video broadcasting; electronic design automation; instruction sets; integrated circuit design; random-access storage; read-only storage; ASIP design; ICORE; ISS-Core; Infineon Technologies; RAM; ROM; application specific instruction set processors; digital video broadcasting algorithms; full-custom DSP core; memory models; optimized instruction encoding; power efficient semi-automatic instruction encoding; read only memories; semi-automatic hardware instruction generation; Application software; Application specific processors; Casting; Design methodology; Digital signal processing; Encoding; Hardware; Instruction sets; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on

Conference_Location

Salt Lake City, UT

ISSN

1520-6149

Print_ISBN

0-7803-7041-4

Type

conf

DOI

10.1109/ICASSP.2001.941131

Filename

941131