A fractional-N DPLL with adaptive spur cancellation and calibration-free injection-locked TDC in 65nm CMOS

A robust and low-cost fractional-N digital phase locked loop (DPLL) architecture is demonstrated via the proposed adaptive spur cancellation schemes and calibration-free time-to-digital converter (TDC). By leveraging the injection locked ring oscillator, the TDC achieves a fine resolution of ~7 ps that automatically tracks the period of digital controlled oscillator (DCO) and hence no TDC gain calibration is required over PVT. To suppress the spurious tones due to external or internal interferences, a gradient-based adaptive spur cancellation scheme is proposed and demonstrated more than 40 dB improvement in the lab measurement. The proof-of-concept DPLL prototype is implemented in 65 nm CMOS and synthesizes frequencies between 2.7 to 4.8 GHz with fine frequency resolution of 610 Hz. The measured phase noise is -130 dBc/Hz at 3 MHz offset and the reference spur achieves -86.45 dBc.