Title :
Power-aware partitioned cache architectures
Author :
Kim, S. ; Vijaykrishnan, N. ; Kandemir, M. ; Sivasubramaniam, A. ; Irwin, M.J. ; Geethanjali, E.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Focuses on partitioning the cache resources architecturally for energy and energy-delay optimizations. Specifically, we investigate ways of splitting the cache into several smaller units, each of which is a cache by itself (called subcache). Subcache architectures not only reduce the per-access energy costs but can potentially improve the locality behavior as well. We present a unified framework for designing, implementing and evaluating different subcache architectures. Different techniques for data placement, subcache prediction, and selective probing are proposed and evaluated using a diverse set of applications. The results show that intelligent subcache mechanisms proposed in this paper are effective
Keywords :
cache storage; delays; low-power electronics; memory architecture; data placement; energy optimizations; energy-delay optimizations; locality behavior; partitioned cache resources; per-access energy costs; power-aware architectures; selective probing; subcache architectures; subcache prediction; Capacitance; Circuits; Computer architecture; Computer science; Energy consumption; Hardware; Permission; Power engineering and energy; Space exploration; Wiring;
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
DOI :
10.1109/LPE.2001.945374