Effects of elevated temperature on tunable near-zero threshold CMOS

This paper explores functionality, performance, and energy efficiency of an 80,000 transistor, 0.35 μm, back-bias tunable, near-zero V_th, 32×32-bit multiplier operating at 100°C. Compared to operation at 28°C, performance at V_dd =2.0 V degrades 14 percent from 188 MHz to 162 MHz. At lower supply voltages, back bias is adjusted to minimize power dissipation as a function of operating frequency similarly to what we reported last year at 28°C. Comparing the operating points, the same performance at 100°C requires about 1.5 times the power measured at 28°C. It also requires about 1.2 V additional back bias and about a 20 percent increase in V_dd. The fraction of total power dissipated as leakage increases by about 1.5 times