Ultra-low power DLMS adaptive filter for hearing aid applications

We present an ultra-low power DLMS (delayed least mean square) adaptive filter working in the sub-threshold region for hearing aid applications. Sub-threshold operation was accomplished by using a parallel architecture with pseudo NMOS logic style. The parallel architecture enabled us to run the system at a lower clock rate with a reduced supply voltage, while maintaining the same throughput. Pseudo NMOS logic operating in the sub-threshold region (Sub-Pseudo NMOS) provided better power-delay product than subthreshold CMOS (Sub-CMOS) logic. Simulation results show that the system can process voice signals at a throughput of 22 kHz with a supply voltage of 400 mV and achieve 91% improvement in energy compared to the non-parallel architecture using standard CMOS logic