Title :
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU
Author :
Miura, Seiji ; Ayukawa, Kazushige ; Watanabe, Takao
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40% and latency by 38% compared to those of standby mode. An SDRAM controller was developed based on this scheme and 0.18 μm CMOS technology. The area of the controller is 0.28 mm2 and its operating current is 2.5 mA at 1.8 V and 100 MHz
Keywords :
CMOS digital integrated circuits; DRAM chips; high-speed integrated circuits; low-power electronics; microprocessor chips; reduced instruction set computing; 0.18 micron; 1.8 V; 100 MHz; 2.5 mA; 32 bit; CMOS technology; RISC CPU; SDRAM controller; active standby mode; dynamic-SDRAM-mode-control scheme; latency reduction; low-power systems; operating current reduction; standby mode; synchronous DRAM; CMOS technology; Circuits; Delay; Laboratories; Permission; Personal communication networks; Personal digital assistants; Random access memory; Reduced instruction set computing; SDRAM;
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
DOI :
10.1109/LPE.2001.945432
