Title :
A dual-mode highly efficient 60 GHz power amplifier in 65 nm CMOS
Author :
Farahabadi, Payam M. ; Moez, Kambiz
Author_Institution :
iCAS Lab., Univ. of Alberta, Edmonton, AB, Canada
Abstract :
This paper presents a 60 GHz power amplifier utilizing a novel technique to achieve high efficiency at high output power levels. The proposed topology provides the capability of dual mode operation. The output power of a conventional class A power amplifier will be combined with the power provided by an amplifier operating at a different class to achieve higher efficiency at higher output levels. Driver stages to provide high power gain consist of an enhanced cascode stage followed by a common source amplifier with transformer-coupled impedance matching networks. Fabricated in 65 nm CMOS process, the measured gain of the 0.32 mm2 power amplifier is 17.7 dB at 60 GHz with a wide 3dB band width of 12 GHz while consuming 378 mW from a 1.2V supply. A maximum saturated output power of 16.8 dBm is measured with the 14.5% peak power added efficiency at 60 GHz.
Keywords :
CMOS analogue integrated circuits; impedance matching; millimetre wave integrated circuits; millimetre wave power amplifiers; CMOS process; bandwidth 12 GHz; cascode stage enhancement; class A power amplifier; common source amplifier; dual-mode highly efficient power amplifier; efficiency 14.5 percent; frequency 60 GHz; gain 17.7 dB; power 378 mW; power levels; size 65 nm; transformer-coupled impedance matching networks; voltage 1.2 V; CMOS integrated circuits; Fingers; Gain; Power amplifiers; Power generation; Power measurement; Transistors; 60 GHz wireless communication; CMOS power amplifier; power added efficiency;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2014 IEEE
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3862-9
DOI :
10.1109/RFIC.2014.6851684