Title :
State parallel Viterbi decoder soft IP and its applications
Author :
Choi, Sung-Han ; Kong, JunJi
Author_Institution :
Samsung Adv. Inst. of Technol., Suwon, South Korea
Abstract :
This paper covers the state parallel Viterbi decoder soft IP (intellectual property) and its applications. We have designed a reusable soft IP of parallel structure Viterbi decoder. It can automatically generate synthesizable Verilog-HDL source codes of the Viterbi decoder and convolutional encoder, synthesis scripts and a simple testbench with user defined parameters. The Viterbi decoder core generated from the IP has state-parallel structure with path memory of register exchange type. It is applied successfully to the FEC (forward error correction) of the wideband direct sequence CDMA (code division multiple access) satellite communication system and the TCM (trellis coded modulation) demodulator of the cable modem system
Keywords :
Viterbi decoding; code division multiple access; convolutional codes; demodulators; forward error correction; hardware description languages; industrial property; satellite communication; source coding; trellis coded modulation; FEC; TCM; Verilog-HDL source codes; automatic generation; cable modem system; code division multiple access; convolutional encoder; demodulator; forward error correction; register exchange path memory; reusable soft intellectual property; satellite communication system; state parallel Viterbi decoder; synthesis scripts; testbench; trellis coded modulation; user defined parameters; wideband direct sequence CDMA; Automatic testing; Convolutional codes; Decoding; Forward error correction; Hardware design languages; Intellectual property; Multiaccess communication; Registers; Viterbi algorithm; Wideband;
Conference_Titel :
TENCON 2001. Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology
Print_ISBN :
0-7803-7101-1
DOI :
10.1109/TENCON.2001.949613
